The present invention relates generally to analysis of a hardware device in connection with a computer system. More specifically, the present invention relates to a logic analyzer that is automatically embedded within a hardware device for purposes of debugging.
In the field of electronics, various electronic design automation (EDA) tools are useful for automating the process by which integrated circuits, multi-chip modules, boards, etc., are designed and manufactured. In particular, electronic design automation tools are useful in the design of standard integrated circuits, custom integrated circuits (e.g., ASICs), and in the design of custom configurations for programmable integrated circuits. Integrated circuits that may be programmable by a customer to produce a custom design for that customer include programmable logic devices (PLDs). Programmable logic devices refer to any integrated circuit that may be programmed to perform a desired function and include programmable logic arrays (PLAs), programmable array logic (PAL), field programmable gate arrays (FPGA), complex programmable logic devices (CPLDs), and a wide variety of other logic and memory devices that may be programmed. Often, such PLDs are designed and programmed by a design engineer using an electronic design automation tool that takes the form of a software package.
In the course of generating a design for a PLD, programming the PLD and checking its functionality on the circuit board or in the system for which it is intended, it is important to be able to debug the PLD because a design is not always perfect the first time. Before a PLD is actually programmed with an electronic design, a simulation and/or timing analysis may be used to debug the electronic design. However, once the PLD has been programmed and is operating within a working system, it is also important to be able to debug the PLD in this real-world environment.
And although a simulation may be used to debug many aspects of a PLD, it is nearly impossible to generate a simulation that will accurately exercise all of the features of the PLD on an actual circuit board operating in a complex system. For example, a simulation may not be able to provide timing characteristics that are similar to those that will actually be experienced by the PLD in a running system; e.g., simulation timing signals may be closer or farther apart than what a PLD will actually experience in a real system.
In addition to the difficulties in generating a comprehensive simulation, other circuit board variables such as temperature changes, capacitance, noise, and other factors may cause intermittent failures in a PLD that are only evident when the PLD is operating within a working system. Still further, it can be difficult to generate sufficiently varied test vectors to stress the PLD design to the point where most bugs are likely to be observed. For example, a PLD malfunction can result when the PLD is presented with stimuli that the designer did not expect, and therefore did not take into account during the design and simulation of the PLD. Such malfunctions are difficult to anticipate and must be debugged in the context of the complete system. Thus, simulation of an electronic design is useful, but usually cannot debug a PLD completely.
One approach to debugging a hardware device within a working system is to use a separate piece of hardware equipment called a logic analyzer to analyze signals present on the pins of a hardware device. (For example, the HP1670A Series Logic Analyzer from Hewlett-Packard Company.) Typically, a number of probe wires are connected manually from the logic analyzer to pins of interest on the hardware device in order to monitor signals on those pins. The logic analyzer captures and stores these signals. However, the use of an external logic analyzer to monitor pins of a hardware device has certain limitations when it comes to debugging such a device. For example, such an external logic analyzer can only connect to and monitor the external pins of the hardware device. Thus, there is no way to connect to and monitor signals that are internal to the hardware device. Unfortunately, when programming a hardware device such as a PLD, it would be useful to be able to monitor some of these internal signals in order to debug the PLD.
Although some custom hardware devices may come ready made with some internal debugging hardware, this debugging hardware is typically hardwired to route specific internal signals and cannot be readily changed by an engineer who wishes to look at other signals. Also, with such built-in debugging it is not possible to choose any signal to monitor that the engineer desires, nor can triggering signals and triggering conditions be changed by the engineer. Because a PLD by its very nature is a programmable device that an engineer is attempting to program to perform a particular function, it is important to the engineer to be able to customize monitored signals, trigger signals, and trigger conditions in order to efficiently debug any particular device. Further, creating an electronic design for a PLD is an iterative process that requires creative debugging by an engineer who may wish to view almost any internal signal, and who may change his mind fairly frequently in the course of debugging a PLD within a system. Known external and internal logic analyzers do not provide this flexibility.
A further drawback to using an external logic analyzer or hardwired predetermined debugging hardware inside of a custom chip is that often the number of internal signals that an engineer desires to monitor are greater than the number of available pins on the device. For example, if there are sixteen internal signals that an engineer wishes to monitor on a device, he is unable to do this using an external logic analyzer if the device has only four pins available for debugging.
In some cases, it is possible for an engineer to employ a conventional logic analyzer to study an internal signal of a PLD. This may be accomplished by, for example, an engineer modifying his design so that a normally internal signal is routed temporarily to an output pin of the PLD. The design is then recompiled. The engineer then attaches a probe to this output pin in order to monitor the xe2x80x9cinternalxe2x80x9d signal. Unfortunately, the engineer must recompile his design and reprogram the PLD in order to view this internal signal. Also, when debugging is complete, the engineer must again rewrite the design to remove the internal signal from the output pin, recompile the design and finally reprogram the PLD again. This can be a tedious process.
Even if an engineer is successful in routing an internal signal to an output pin of a PLD, with certain integrated circuit packages it may be extremely difficult to attach an external logic analyzer. For an integrated circuit in a dual in-line package it may be relatively straightforward to attach the probes of a logic analyzer to the top of the package as long as the package is in an easily accessible location on a circuit board. However, if the package is in a difficult to reach location because of device crowding, it may be difficult to physically attach logic analyzer probes to particular output pins of interest. Even more troublesome are integrated circuits with rows of miniature contacts located on the top of the package (e.g., xe2x80x9cflip chipsxe2x80x9d). It is difficult to attach logic analyzer probes to particular outputs of interest with this type of package. Some integrated circuit are encased in a ball grid array package with the contacts located on the bottom of the package up against the circuit board; for these packages, it may be nearly impossible to attach logic analyzer probes to these small contacts located on the underside of the package. Thus, use of an external logic analyzer has shortcomings even if an internal signal can be routed to a pin of a device.
U.S. patent application Ser. No. 08/958,435 entitled xe2x80x9cEmbedded Logic Analyzer For A Programmable Logic Devicexe2x80x9d discloses an advantageous apparatus and techniques that allow an embedded logic analyzer to flexibly analyze internal signals of interest in an electronic design, such as within a programmable logic device (PLD). Nevertheless, there is room for improvement in the analysis of internal signals of a PLD for debugging purposes.
For example, some logic analyzers allow a user to specify a trigger condition and a set of trigger signals that must satisfy that trigger condition before the logic analyzer is triggered into the capture of data. Such logic analyzers are useful when it is desirable to capture and analyze signal data that occurs immediately after a particular trigger condition (such as a failure of the device). It is often desirable, however, to capture signals for later analysis that occur before the trigger condition. For the most part, these logic analyzers that begin data capture based upon satisfaction of a trigger condition are unable to provide captured signals before the trigger condition because the logic analyzer is only designed to begin capture upon an error, failure or other trigger condition. Because these errors and/or failures are unanticipated, these type of logic analyzers are unable to anticipate the trigger condition, and hence, are unable to begin capturing data before the trigger condition occurs.
In some debugging situations, it can be extremely advantageous to capture signals that occur before the trigger conditions occurs. For example, when debugging a PCI bus interface, a situation may occur in which the interface enters an illegal state. Traditional logic analyzers would be able to detect that illegal state and immediately begin capturing signal data for later analysis. It would be extremely desirable, however, to begin capturing signal data before the bus interface enters the illegal state in order to determine why the bus has entered this illegal state. In another example, when an interrupt occurs, it can be extremely desirable to know the history of certain registers before the interrupt occurs. In other words, once the interrupt is received, data capture may begin, but the registers may already be in an incorrect state. It would be extremely desirable to be able to capture and analyze signal data before the interrupt occurs in order to determine why certain registers are in an incorrect state when the interrupt occurs. Other situations in which it would be desirable to capture signal data before a specific trigger condition are also possible.
Various prior art efforts present partial solutions, but each have their drawbacks. For example, external logic analyzers available from the Hewlett-Packard Company allow capture of signal data before a trigger condition (or breakpoint) occurs. Unfortunately, these external logic analyzers suffer from many of the disadvantages associated with external logic analyzers discussed above. Actel Corporation of Sunnyvale, Calif. provides two probes within a programmable logic device that are able to monitor two different signals, but these signals must be prespecified by the user and may not be flexibly reassigned to other signals. In addition, the Actel probes provide constant monitoring of particular signals, but do not allow capture of relevant signal data in relation to a specified breakpoint.
Therefore it would be desirable to have an apparatus and technique that would allow a logic analyzer embedded within a programmable logic device to flexibly capture internal signals both before and after a specified breakpoint.
Furthermore, it would be desirable to have an apparatus and technique that would efficiently and flexibly control a logic analyzer embedded within a programmable logic device. As explained below, although various options are available for controlling such an embedded logic analyzer, none of the prior art techniques are optimal. By way of background, a brief explanation of the design and manufacturing phases of a PLD and a circuit board will be provided first.
As described earlier in this section, a design engineer designs a PLD and programs such a device using an electronic design automation tool. In the course of this design phase, the design engineer may perform numerous design-program-debug iterations before the design is complete and the PLD ready for mass manufacturing. The design engineer often uses a simulation and/or a timing analysis to assist in debugging the electronic design of the PLD. It is also conceivable that a design engineer would use an embedded logic analyzer (such as disclosed in U.S. patent application Ser. No. 08/958,435) to troubleshoot the design. Once the design of the PLD is complete to the design engineer""s satisfaction, the design is handed off to a product engineer for the manufacturing phase.
In the manufacturing phase, a product engineer designs a manufacturing flow for the mass production of an electronic circuit board or other electronic device that incorporates one or more PLDs. During the manufacturing phase, it will be necessary to test the board itself and may also be necessary to retest the PLD. In the beginning of the manufacturing phase, any number and type of hardware components and any number of PLDs are soldered to a board. Once on the board, a PLD is most often programmed (or configured) using a JTAG port located on the PLD. It is also possible that a particular PLD be programmed by itself before placement on a board using a special socket and a programming unit.
A full board test may then be performed to test the traces, solder connections, and other physical interfaces between components on the board. It should be pointed out that a board test may also be performed before any devices on the board are programmed or configured. It is common to use a JTAG port of a PLD or other device to test the traces and solder connections of a board during this board test. Once physical connections are tested, a complete functional test of the board is then formed to test the overall functionality of the board (i.e., to ensure that particular inputs produce the outputs expected). At this point, if a failure is detected it may be necessary to debug a particular PLD while on the board. For failures more difficult to track down, it may even be necessary to remove a PLD from the board to be debugged. In these circumstances, as previously explained, it is desirable to have an embedded logic analyzer within the PLD to facilitate debugging. During any debugging of the PLD using an embedded logic analyzer, it is necessary in some fashion to control the embedded logic analyzer, i.e., to provide it with commands and data and to receive captured data and status from it. Although various options are available, none are currently optimal.
For example, it may be possible to use existing input/output pins of a device to provide a control interface. Unfortunately, a particular design may not have enough extra input/output pins available through which an interface can be provided to control an embedded logic analyzer. It can be undesirable to require that a customer purchasing a PLD not use a certain number of input/output pins simply because the PLD may not have been designed correctly and might have to be debugged at some point.
Intel Corporation of Santa Clara, Calif. uses a JTAG port to control access to specified debug registers for help in debugging a central processing unit (CPU). Because a CPU is a known design, it is known beforehand exactly how many debug registers will be needed and control is simpler. With a PLD, however, each user-implemented design will be custom; it is unknown ahead of time what that design will be and how many debug registers might be needed. Different designs will require different debug registers. Thus the straightforward technique used by Intel with a known design of a CPU would not be appropriate with a PLD.
Therefore, an apparatus and technique are further desirable that would provide simple, efficient and flexible control of an embedded logic analyzer. It would further be desirable for such a control apparatus and technique to allow testing of a PLD on a circuit board in a real-world environment.
To achieve the foregoing, and in accordance with the purpose of the present invention, a technique for embedding a logic analyzer in a programmable logic device is disclosed that allows capture of specified signal data both before and after a specified breakpoint. Also disclosed are techniques for controlling an embedded logic analyzer using a JTAG port.
The present invention provides both an apparatus and a technique by which a logic analyzer circuit is automatically embedded within a PLD, by which it captures and stores logic signals both before and after a breakpoint, and by which it unloads these signals through an interface to a computer. In a preferred embodiment, analysis of the signals is performed on the computer, with the xe2x80x9con-chipxe2x80x9d logic analyzer circuit serving only to acquire the signals. The invention works especially well with a PLD because, by its very nature, a PLD is able to be programmed with a design, the design may be changed, and the PLD programmed again and again. Thus, the logic analyzer circuit may be embedded in test designs or iterations in the process of designing a final PLD. Upon successful debugging of the PLD design, the PLD chip can be reprogrammed without the logic analyzer circuit, or the circuit can be left on the chip.
In one embodiment of the invention, using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, specifies the number of samples to be captured, specifies a system clock signal, and specifies not only a breakpoint, but also the number of samples needed prior to the breakpoint. (Alternatively, total samples could be specified and/or samples needed after a breakpoint.) The EDA tool then automatically inserts the logic analyzer circuit into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool communicates with the embedded logic analyzer in order to instruct the logic analyzer to run and to begin capturing data. Once a breakpoint occurs, the logic analyzer determines if more samples need to be captured after the breakpoint. The EDA tool then directs the logic analyzer to unload the data from sample memory and then displays the data on the computer. The logic analyzer circuit may then run again to capture another sequence of sample values.
In one specific embodiment of the invention, the logic analyzer captures data from specified signal lines continuously in a ring buffer, or similar memory structure that overwrites earlier stored data when full. In this fashion, relevant data is stored continuously before a breakpoint occurs, thus, the stored data may be viewed later by a user who wishes to view signals occurring before the breakpoint. Once the breakpoint occurs, a counter keeps track of how many additional samples of data (if any) need be collected.
Often, a JTAG port is used either to program a PLD or to assist with testing a circuit board on which PLDs are located. Advantageously, it is realized that a JTAG port has traditionally been unused during the design and debugging of a particular PLD. Thus, it is further realized that a JTAG port on a PLD is under utilized and may be used during debugging of a PLD as a means of communicating with and controlling an embedded logic analyzer of the present invention. Advantageously, the standard JTAG port is used to facilitate debugging of a programmable logic device that includes an embedded logic analyzer. Use of a JTAG port avoids adding dedicated debugging control pins. In a first embodiment for controlling an embedded logic analyzer using a JTAG port, inputs and outputs of the logic analyzer are routed to unbonded JTAG-enabled I/O cells. Cells that will provide control signals are tricked into thinking they are in INTEST mode so that signals may be input, yet the rest of the device operates as in a real-world environment. In a second embodiment, a user-implemented test data register provides a JTAG-like chain of logic elements through which control and output information is shifted. Stimulus cells provide control information to the logic analyzer, and sense cells retrieve data from the logic analyzer.
The present invention provides many advantages over the prior art. Use of an embedded logic analyzer in a PLD allows debugging of the device in the system in which it is operating and under the actual conditions that might produce a malfunction of the PLD. The technique of the present invention automatically embeds a logic analyzer circuit into a PLD so that an engineer may debug any logic function within the device. The embedded logic analyzer is able to capture any internal signals specified by the engineer; the breakpoint can also include any specified internal signals. Through the use of memory within the embedded logic analyzer and an interface to the computer, any number and depth of signals can be monitored within the device and then transmitted to the computer at a later time for analysis. In one embodiment of the invention, a JTAG port is used to program the embedded logic analyzer and to transmit captured signal information to the computer.
Advantageously, while debugging a PLD design in a system, an engineer may use the EDA tool to specify new signals to monitor and/or new breakpoints. The engineer can then reprogram the device while it is within its intended system with a modified logic analyzer circuit very rapidly in order to debug a different portion of the device or to change the triggering conditions. This ability to reprogram an embedded logic analyzer on the fly has many advantages over built-in debugging hardware on custom chips that may not be dynamically reprogrammed. This ability to reprogram also has advantages over external logic analyzers that can only monitor the external pins of a hardware device. Furthermore, once an engineer has finished debugging the device with the embedded logic analyzer, the EDA tool may be used to generate a final configuration output file without the logic analyzer that represents the engineer""s final working design. Thus, the logic analyzer need not be part of the final design and take up space on the PLD.
The present invention is applicable to a wide range of hardware devices, and especially to PLDs. A PLD in particular may be implemented using a wide variety of technologies, including SRAM technology and EEPROM technology. PLDs based upon SRAM technology are especially advantageous in that they may have additional embedded memory that can be used by the embedded logic analyzer to capture a large number of, and a greater depth of signals. Furthermore, an embedded logic analyzer that is designed and inserted automatically by an EDA tool means that an engineer does not require an external logic analyzer as a separate piece of equipment. Furthermore, the engineer may use the computer on which he or she is creating a design for the PLD to also control and configure the embedded logic analyzer and to review its results.
In one embodiment of the present invention, a number of pins on the PLD are dedicated interface pins for communication with the user computer. Because these pins are dedicated for the interface, and are known ahead of time, they may be routed to an easily accessible location or port on a circuit board, such that a debugging interface cable may be connected from the user computer to these pins extremely easily. This technique is especially advantageous where pins or contacts of a particular integrated circuit in a package may be difficult or nearly impossible to reach. Because the embedded logic analyzer of the present invention may be configured to monitor any internal or external signals of the PLD, all of these monitored signals are available for analysis through these interface pins. In other words, it is not necessary to physically connect a probe to a particular external pin of interest because any signal within the PLD can be monitored, stored within the memory of the embedded logic analyzer and then later uploaded to the user computer for analysis through these dedicated interface pins.
Additionally, an embedded logic analyzer can be used with PLDs that are configured to near capacity. An engineer can temporarily remove a portion of the design unrelated to the problem under analysis, embed a logic analyzer circuit, and then debug the PLD. Once the PLD has been debugged, the engineer may then remove the embedded logic analyzer and reinsert that section of the design that he had temporarily removed.